1. Field of the Invention
The present invention relates to a semiconductor device and the process thereof and in particular to a trench capacitor process for preventing parasitic leakage adjacent to trench capacitors in DRAM cells.
2. Description of the Related Art
Dynamic random access memory (DRAM), a kind of semiconductor memory, consists of a storage capacitor and an access transistor in each cell enables higher integration, and is widely used in computers and electronic devices.
Nevertheless, charge stored in a capacitor decreases over time, resulting from an inherent leakage current, so DRAM cells must be refreshed before the stored charge falls below the operational threshold voltage (Vth).
A trench capacitor is a typical structure used in DRAM cells, and storage capacity thereof can be increased through enlarging the depth of the trench and providing a larger surface area.
In FIG. 1, a layout is shown for conventional trench capacitors. Trench capacitors 10 are disposed under passing wordlines 12. Access transistors 14 are electrically coupled to storage nodes 16 of trench capacitors 10 through diffusion regions 18. Diffusion regions 20 are also included, being electrically connected to contacts 22. The contacts 22 connect to a bitline (not shown) to read and write to storage nodes 16 through access transistors 14. Access transistors 14 are activated by wordlines 12. When voltage is applied to wordlines 12, a channel therebelow allows current between diffusion regions 18 and 20 and into or out of storage nodes 16.
In FIG. 2, a cross-section along the A-A′ phantom line in FIG. 1 is shown to illustrate a conventional trench capacitor employed in n-channel MOSFET. At this point, a trench capacitor 10 is formed in a substrate 24 and the trench is typically filled with polysilicon to form a storage node 16 doped with n-type dopants. A buried plate 26 is also doped with n-type dopants and surrounds the lower portion of the trench. A node dielectric 28 separates the storage node 16 and the buried plate 26. The storage node 16 and a P-well PW, including p-dopants are electrically isolated by the dielectric collars 30. The buried well 32, including n-type dopants, is provided to connect the buried plate 26 adjacent to the trench capacitor 10.
The diffusion region 18 of the access transistor 14 is connected to the storage node 16 by a node diffusion region 34. When the trench capacitor 10 is completely formed, a shallow trench isolation (STI) 38 is then formed in the substrate and part of the trench capacitor 10 to define an active area and to isolate the trench capacitor 10 and a passing wordline 12′ formed later. Wordlines 12 and the STI 38 can then be used as implant masks forming diffusion regions 18 and 20 which may be a source and drain of the access transistor 14.
During the operation of the trench capacitor 10, a vertical parasitic transistor will typically be formed on the sidewall of the trench in the region 40 of FIG. 2, located in the p-well PW between the node diffusion region 34 and the buried plate 24.
The region 40 in FIG. 2 is further enlarged and rotated 90° counterclockwise in FIG. 3 for illustration. At this point, the above-mentioned parasitic transistor includes the node diffusion region 34 and the buried well 32 as its source and drain (respectively). When an appropriate charge is stored within the capacitor, the storage node 16 acts as a gate and the dielectric collar 30 acts as a gate dielectric, and then a channel 42 will be formed in the p-well PW within the substrate and charges stored in a trench capacitor can pass through this channel 42 and form a parasitic leakage current, resulting in increased frequency to refresh the storage capacitor and affect charge storage performance.